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[VHDL-FPGA-Verilog] wave_genarator_vhdl

Description: vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.
Platform: | Size: 10240 | Author: 江汉 | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[Other] fqdiv

Description: 能够实现0~99的任意分频,并实现输出频率50％的占空比-0 ~ 99 to realize the arbitrary frequency and to achieve an output frequency of 50 duty cycle
Platform: | Size: 98304 | Author: 杨苏 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 利用VHDL语言实现FPGA的PWM输出波形，占空比可控-FPGA using VHDL language realize the PWM output waveform, duty cycle controlled
Platform: | Size: 36864 | Author: 王传辉 | Hits:

[VHDL-FPGA-Verilog] division

Description: 很实用的一个分频带码，包括奇分频，偶分频，占空比为50％的奇分频,实际工程中很实用-Very useful to a sub-band code, including the odd sub-frequency, dual frequency, duty cycle 50 of the odd sub-frequency, the actual works in very practical
Platform: | Size: 290816 | Author: ecomputer | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
Platform: | Size: 9216 | Author: zhanyi | Hits:

[Other] pwm

Description: 通过改变pwm的占空比，调节LED灯的亮暗程度-By changing the duty cycle pwm, regulating bright LED lights concealed the extent of
Platform: | Size: 209920 | Author: liupeinan | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] fen1to7

Description: 这是我在ISP编程实验中独立编写的一个采用行为描述方式实现的分频器，通过两个并行进程对输入信号CLK进行8分频，占空比为1:7-This is my ISP programming experiment in the preparation of an independent description of the use of behavior to achieve the prescaler, through two parallel processes on the input signal CLK to 8 minutes frequency, duty cycle 1:7
Platform: | Size: 27648 | Author: daisichong | Hits:

[VHDL-FPGA-Verilog] cepin

Description: 本频率计具有测周、测频、测量占空比等基本功能，能自动换档-The frequency meter has a measurement weeks, measuring frequency, measuring the basic functions of duty cycle, etc., can automatic transmission
Platform: | Size: 690176 | Author: 唐光敏 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[Software Engineering] BasedonCPLDFPGAsuchasthefrequencyaccuracyofthedesi

Description: 基于CPLD／FPGA的可编程逻辑器件，借助单片机AT89C51；利用标准频率50～100MHz的周期信号实现系统计数的等精度测量技术。同时采用闸门测量技术完成脉宽,占空比的测量。-Based on CPLD/FPGA programmable logic devices, with single-chip microcomputer AT89C51 using a standard 50 ~ 100MHz frequency of the periodic signal, such as counting the realization of the system measurement accuracy. Measurement techniques used to complete the gate pulse width, duty cycle measurements.
Platform: | Size: 179200 | Author: 何蓓 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.-Realization of PWM wave generation, can be used for motor control. Can change its duty cycle and frequency to achieve the speed control motor.
Platform: | Size: 436224 | Author: 宋瑞鹏 | Hits:

[VHDL-FPGA-Verilog] 1

Description: 多功能波形发生器 方波（占空比可调） 三角波 -Multi-function waveform generator square wave (variable duty cycle) triangular wave
Platform: | Size: 1024 | Author: wanghua | Hits:

[SCM] pwm

Description: pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Platform: | Size: 1024 | Author: chenhaoran | Hits:

[SCM] xinhao001

Description: 产生正弦波、方波、锯齿波，频率可调，方波占空比可调-Generated sine wave, square wave, sawtooth wave, frequency adjustable, adjustable duty cycle square wave
Platform: | Size: 2963456 | Author: wangyang | Hits:

[VHDL-FPGA-Verilog] ktf

Description: 这是一个用VHDL编写的占空比可调的程序，对一个刚刚入门的FPGA的学员来说可以起到一个引导作用，简单但能学到很多东西-This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot
Platform: | Size: 1024 | Author: wangkai | Hits:

[VHDL-FPGA-Verilog] fequency

Description: 基于CPLD的等精度数度频率计，可以通过外设功能按键实现，频率、相位、占空比等参数的测量。-CPLD based on the number of degrees of accuracy, such as frequency meter, key peripheral functions can be achieved, frequency, phase, duty cycle measurement of parameters such as
Platform: | Size: 380928 | Author: dzt | Hits:

[VHDL-FPGA-Verilog] Multi_function_waveform_generator

Description: 多功能波形发生器VHDL程序与仿真.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Multi-function waveform generator and simulation of VHDL procedures. The realization of four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and magnitude of control output (square wave of duty cycle A is controllable), Arbitrary Waveform characteristics can store data and can reproduce the waveform, but also the completion of the linear superposition of a variety of output waveforms.
Platform: | Size: 10240 | Author: | Hits:

[SCM] PWM

Description: 四路PWM输出控制器，输入频率5OMHz，输出频率调，输入数据实现占空比控制。-Four-way controller PWM output, input frequency 5OMHz, tune output frequency, duty cycle control of the realization of the input data.
Platform: | Size: 238592 | Author: wx | Hits:
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